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| SPANSION Flash Memory Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20910-1E BURST MODE FLASH MEMORY CMOS 128M (8M x 16) BIT MBM29BS/FS12DH 12 s DESCRIPTION The MBM29BS/FS12DH is a 128 Mbit, 1.8 Volt-only, Burst mode and dual operation Flash memory organized as 8M words of 16 bits each. The device offered in a 80-ball FBGA package. This device is designed to be programmed in-system with the standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Handshaking On/Off Ordering Part No. VCC = 1.8 V CLK Freq. : 80 MHz (-12) Max Latency (even address in case of Handshaking) Time (ns) Synchronous/Burst Max Burst Access Time (ns) Max OE Access Time (ns) Max Address Access Time (ns) Asynchronous Max CE Access Time (ns) Max OE Access Time (ns) +0.15 V -0.15 V MBM29BS12DH Non-Handshaking 12 58.5 8.5 8.5 45 45 8.5 MBM29FS12DH Handshaking 12 46 8.5 8.5 45 45 8.5 s PACKAGE 80-ball plastic FBGA (BGA-80P-M04) MBM29BS/FS12DH12 (Continued) The device provides truly high performance non-volatile memory solution. The device offers fast burst access frequency of 80 MHz with initial access times of 46 ns at Handshaking mode, allowing operation of high-speed microprocessors without wait states. To eliminate bus connection the device has separate chip enable (CE), write enable (WE), address valid (AVD) and output enable (OE) controls. For burst operations, the device additionally requires Ready (RDY) at Handshaking mode, and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/ microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space. At 80 MHz, the device provides a burst access of 8.5 ns with a latency of 46 ns at 30 pF (Handshaking mode). The dual operation function provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The Enhanced VI/O (VCCQ) feature allows the output voltage generated on the device to be determined based on the VI/O level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 MBM29BS/FS12DH12 s FEATURES * * * * 0.13 m process technology Single 1.8 V read, program and erase (1.65 V to 1.95 V) Simultaneous Read/Write operation (Dual Bank) FlexBankTM*1 Bank A: 16 Mbit (4 Kwords x 8 and 32 Kwords x 31) Bank B: 48 Mbit (32 Kwords x 96) Bank C: 48 Mbit (32 Kwords x 96) Bank D: 16 Mbit (4 Kwords x 8 and 32 Kwords x 31) Enhanced VI/OTM*2 (VCCQ) Feature Input/ Output voltage generated on the device is determined based on the VI/O level High Performance Burst frequency reach at 80 MHz Burst access times of 8.5 ns @ 30 pF at industrial temperature range Asynchronous random access times of 45 ns (at 30 pF) Synchronous latency of 46 ns with 1.8 V VCCQ for Handshaking mode Programmable Burst Interface Linear Burst: 8, 16, and 32 words with wrap-around Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Minimum 100,000 program/erase cycles Sector Erase Architecture Eight 4 Kwords, two hundred fifty-four 32 Kwords sectors, eight 4 Kwords sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase. HiddenROM region 64 words for factory and 64 words for customer of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a sector secure serial number (ESN) Write Protect Pin (WP) At VIL, allows protection of "outermost" 4x4 K words on low, high end or both ends of boot sectors, regardless of sector protection/unprotection status Accelerate Pin (ACC) At VACC, increases program performance. ; all sectors locked when ACC = VIL Embedded EraseTM*2 Algorithms Automatically preprograms and erases the chip or any sector Embedded ProgramTM*2 Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready Output (RDY) In Synchronous Mode, indicates the status of the Burst read. In Asynchronous Mode, indicates the status of the internal program and erase function. Automatic sleep mode When address remain stable, the device automatically switches itself to low power mode Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device In accordance with CFI (Common Flash Interface) Hardware reset pin (RESET) Hardware method to reset the device for reading array data * * * * * * * * * * * * * * * * * *1 : FlexBankTM is a trademark of Fujitsu Limited. *2 : Embedded EraseTM, Embedded ProgramTM and Enhanced VI/OTM are trademarks of Advanced Micro Devices, Inc. (Continued) 3 MBM29BS/FS12DH12 (Continued) * Sector Protection Persistent sector protection Password sector protection ACC protects all sectors WP protects the outermost 4 x 4 K words on both ends of boot sectors, regardless of sector protection / unprotection status. * Handshaking feature available (MBM29FS12DH) Provides host system with minimum possible latency by monitoring RDY * CMOS compatible inputs, CMOS compatible outputs 4 MBM29BS/FS12DH12 s PIN ASSIGNMENT FBGA (TOP VIEW) Marking Side A8 N.C. A7 N.C. B8 N.C. B7 N.C. C8 N.C. C7 A13 C6 A9 C5 WE C4 RDY C3 A7 A2 N.C. A1 N.C. B2 N.C. B1 N.C. C2 A3 C1 N.C. D8 A22 D7 A12 D6 A8 D5 RESET D4 ACC D3 A17 D2 A4 D1 VCC E8 N.C. E7 A14 E6 A10 E5 A21 E4 A18 E3 A6 E2 A2 E1 CLK F8 VCCQ F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 F1 WP G8 VSSQ G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 G1 AVD H8 N.C. H7 N.C. H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE H1 VCCQ J8 N.C. J7 DQ15 J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE J1 VSSQ K8 N.C. K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS K1 N.C. L8 N.C. L7 N.C. M8 N.C. M7 N.C. L2 N.C. L1 N.C. M2 N.C. M1 N.C. (BGA-80P-M04) s PIN DESCRIPTIONS Pin name A22 to A0 DQ15 to DQ0 CLK CE OE WE AVD RDY RESET WP ACC N.C. VSS VCC VSSQ VCCQ MBM29BS/FS12DH Pin Configuration Table Function Address Inputs Data Inputs/Outputs CLK Input Chip Enable Output Enable Write Enable Address Valid Input Ready Output. (In asynchronous mode, RY/BY Output) Hardware Reset Hardware Write Protection Program Acceleration Pin Not Connected Internally Device Ground Device Power Supply Input & Output Buffer Ground Input & Output Buffer Power Supply 5 MBM29BS/FS12DH12 s BLOCK DIAGRAM VCC VSS VCCQ VSSQ A22 to A0 Y-Gating Cell Matrix 16 Mbit (Bank A) X-Decoder Cell Matrix 48 Mbit (Bank B) X-Decoder Bank B Address RESET WE CE OE WP AVD CLK ACC State Control & Command Register RDY Status Control Bank C Address DQ15 to DQ0 X-Decoder Y-Gating Cell Matrix 16 Mbit (Bank D) X-Decoder Cell Matrix 48 Mbit (Bank C) Y-Gating Bank D address s LOGIC SYMBOL 23 A22 to A0 DQ15 to DQ0 CLK WP ACC CE OE WE RESET AVD RDY 16 6 Y-Gating Bank A address MBM29BS/FS12DH12 s DEVICE BUS OPERATION MBM29BS/FS12DH User Bus Operations Table Operation CE OE WE WP ACC A22 to A0 DQ15 to DQ0 CLK AVD RESET Asynchronous Mode Operations (Default) Asynchronous Read Addresses Latched *1 Standby Output Disable Write - WE address latched * 3 3 L H L L L X X X L X H H H X X X H X H L X X X X X X X* X* L X X 2 2 X X X H* H* X L X 2 2 Addr In X X Addr In Addr In X X X DOUT High-Z High-Z DIN DIN X X High-Z X X X X X X X X L X X L X X X H H H H H H H L Write - AVD address latched * All Sector Write Protection *2 RESET Load Starting Burst Address (CLK latch) *1 Boot Block Sector Write Protection *2 Synchronous Mode Operations (need to set the configuration register) L X H X X Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus *1 Terminate current Burst read cycle Terminate current Burst read via RESET Terminate current Burst read cycle and start new Burst read cycle Burst Suspend Standby Output Disable Write - WE address latched *4 Write - CLK address latched *4 Write - AVD address latched * All Sector Write Protection *2 RESET Legend: L = VIL, H = VIH, X = VIL or VIH, 4 2 L H X L L H L L L L X X X L X X X H X H H H H X X X H H H H H X H L X X X X X X X X*2 X*2 X* 2 X X X X X X X H*2 H*2 H* X L X 2 X X X Addr In X X X Addr In Addr In Addr In X X X DOUT High-Z High-Z DOUT High-Z High-Z High-Z DIN DIN DIN X X High-Z H/L X X X X X X H/L X H X X H H L H H X X L H H H H H H Boot Block Sector Write Protection * X X X L X X X X X H H L = Pulse input. See "sDC CHARACTERISTICS" for voltage levels. *1 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *2 : At WP=VIL, SA0-SA3 and SA266-SA269 are protected. At ACC=VIL, all sectors are protected. *3 : Write Operation: at asynchronous mode, addresses are latched on the last falling edge of WE pulse while AVD is held low or rising edge of AVD pulse whichever comes first. Data is latched on the 1st rising edge of WE. *4 : Write Operation: at synchronous mode, addresses are latched on the falling edge of WE while AVD is held low or active edge of CLK while AVD is held low whichever happens first. Data is latched on the 1st rising edge of WE. 7 MBM29BS/FS12DH12 MBM29BS/FS12DH Command Definitions Table Command Sequence Read / Reset Read / Reset Autoselect Program Chip Erase Sector Erase Erase Suspend Erase Resume Set to Fast Mode Fast Program Reset from Fast Mode *1 Set Burst Mode Configuration Register Query HiddenROM Entry HiddenROM Program*2 HiddenROM Exit *2 HiddenROM Protect *2 Password Program Password Unlock First Bus Bus Second Write Write Write Cycle Cycle Cycles Req'd Addr. Data Addr. Data Third Write Fourth Write Fifth Write Sixth Write Cycle Cycle Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Seventh Write Cycle Data Addr. Data 1 3 3 4 6 6 1 1 3 2 2 3 1 3 4 4 6 XXXh F0h RA RD 55h 55h 55h 55h 55h -- 555h (BA) 555h 555h 555h 555h -- F0h 90h A0h 80h 80h -- RA -- RD -- -- -- -- 2AAh 2AAh -- -- -- -- 55h 55h -- -- -- -- 555h SA -- -- -- -- 10h 30h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh BA BA B0h 30h -- PA 555h 555h -- PD AAh AAh -- -- PA -- -- 55h PD -- -- 555h -- -- 20h -- -- -- -- -- -- -- -- (HRA) PA XXXh -- -- -- -- -- -- -- -- PD 00h -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RD (0) 555h AAh 2AAh XXXh BA A0 -- -- (CR) 555h -- -- 90h XXXh F0h*3 555h AAh 2AAh (BA) 55h 55h C0h 98h -- -- 55h 55h 55h 55h 55h 55h 55h 55h 55h -- 555h 555h (HRBA) -- 88h A0h 90h 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 555h 555h 555h 555h 555h 555h 555h 60h OPBP 68h OPBP 48h XXXh 38h 38h 38h 38h 28h XX0h XX1h XX2h XX3h XX0h PD0 PD1 PD2 PD3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 555h AAh 2AAh 555h AAh 2AAh 555h AAh 2AAh 7 555h AAh 2AAh PD0 XX1h PD1 XX2h PD2 XX3h PD3 (Continued) 8 MBM29BS/FS12DH12 (Continued) Command Sequence Password Verify Password Mode Locking Bit Program Persistent Protection Mode Locking Bit Program PPB Program PPB Verify All PPB Erase PPB Lock Bit Set PPB Lock Bit Verify DPB Write DPB Erase DPB Verify Legend: RA PA First Bus Bus Second Third Write Write Write Write Cycle Cycle Cycle Cycles Req'd Addr. Data Addr. Data Addr. Data Fourth Write Cycle Addr. Data Fifth Write Cycle Addr. Sixth Write Cycle Data Seventh Write Cycle Addr. Data Data Addr. 4 6 555h 555h AAh 2AAh AAh 2AAh 55h 55h 555h C8h 555h 60h PWA PWD PL 68h -- PL -- 48h -- XXh -- RD (0) -- -- -- -- 6 555h AAh 2AAh 55h 555h 60h SPML 68h SPML 48h XXh RD (0) RD (0) -- -- 6 4 6 6 4 4 4 4 555h 555h 555h 555h 555h 555h 555h 555h AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh AAh 2AAh 55h 55h 55h 55h 55h 55h 55h 55h 555h (BA) 555h 555h 555h 555h 555h 555h 555h 60h 90h 60h 78h 58h 48h 48h 58h SGA+ WP SGA+ WP WP 68h RD (0) 60h SGA+ 48h WP XXh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- XXh -- RD (0) SGA+ 40h WP -- SA SA SA SA -- RD (1) X1h X0h RD (0) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- = Address of the memory location to be read. = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD pulse or active edge of CLK while AVD = VIL whichever comes first or falling edge of write pulse while AVD = VIL. SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address. Address settled by A22, A21, A20 will select Bank A, Bank B, Bank C and Bank D. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of write pulse. SGA = Sector group address to be protected. SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area 000000h to 00007Fh HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = VIL) RD (0) = Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0 RD (1) = Read Data bit. If programmed, DQ1 = 1, if erase, DQ1 = 0 OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0) PWA/PWD = Password Address/Password Data PL = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0) SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0) WP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0) CR = Configuration Register address bits A19 to A12. (Continued) 9 MBM29BS/FS12DH12 (Continued) *1: This command is valid during Fast Mode. *2: This command is valid during HiddenROM mode. *3: The data "00h" is also acceptable. Notes : * Address bits A22 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA, SGA, OPBP, PWA, PL, SPML, WP, WPH. * Bus operations are defined in "MBM29BS/FS12DH User Bus Operations Table". * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * Command Combinations not described in "MBM29BS/FS12DH Command Definitions Table" are illegal. MBM29BS/FS12DH Sector Protection Verify Autoselect Codes Table A7 A6 A5 A4 A3 A2 A1 A0 Code (HEX) A22 to A12 BA BA BA BA Sector Group Addresses VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIL VIL VIL VIH VIH VIH VIL VIH VIL VIH VIL 04h 227Eh 2218h 2200h 01h*1 Type Device Code Manufacture's Code Extended Device Code*2 Sector Group Protection Indicator Bits BA VIL VIL VIL VIL VIL VIL VIH DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 - Customer Lock Bit VIH 1 = Locked, 0 = Not Locked DQ5 - Handshake Bit 1 = Handshake (FS12), 0 = non-Handshake(BS12) *1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Extended Autoselect Code Table Type Manufacture's Code Device Code Extended Device Code Sector Group Protection Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h 227Eh 2218h 2200h 00h 01h 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 10 MBM29BS/FS12DH12 s FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (Bank A) Sector Address Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 0 0 0 000000 0 0 0 000000 0 0 0 000000 0 0 0 000000 0 0 0 000001 0 0 0 000001 0 0 0 000001 0 0 0 000001 0 0 0 00001X 0 0 0 00010X 0 0 0 00011X 0 0 0 00100X 0 0 0 00101X 0 0 0 00110X 0 0 0 00111X 0 0 0 01000X 0 0 0 01001X 0 0 0 01010X 0 0 0 01011X 0 0 0 01100X 0 0 0 01101X 0 0 0 01110X 0 0 0 01111X 0 0 0 10000X 0 0 0 10001X 0 0 0 10010X 0 0 0 10011X 0 0 0 10100X 0 0 0 10101X 0 0 0 10110X 0 0 0 10111X 0 0 0 11000X 0 0 0 11001X 0 0 0 11010X 0 0 0 11011X 0 0 0 11100X 0 0 0 11101X 0 0 0 11110X 0 0 0 11111X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 06FFFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh Bank A 11 MBM29BS/FS12DH12 Sector Address Table (Bank B) Sector Address Bank Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Bank Address A22 A21 A20 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 Sector Size (x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 0 0 0 0XXX 32 100000h to 107FFFh 0 0 0 0 1XXX 32 108000h to 10FFFFh 0 0 0 1 0XXX 32 110000h to 117FFFh 0 0 0 1 1XXX 32 118000h to 11FFFFh 0 0 1 0 0XXX 32 120000h to 127FFFh 0 0 1 0 1XXX 32 128000h to 12FFFFh 0 0 1 1 0XXX 32 130000h to 137FFFh 0 0 1 1 1XXX 32 138000h to 13FFFFh 0 1 0 0 0XXX 32 140000h to 147FFFh 0 1 0 0 1XXX 32 148000h to 14FFFFh 0 1 0 1 0XXX 32 150000h to 157FFFh 0 1 0 1 1XXX 32 158000h to 15FFFFh 0 1 1 0 0XXX 32 160000h to 167FFFh 0 1 1 0 1XXX 32 168000h to 16FFFFh 0 1 1 1 0XXX 32 170000h to 177FFFh 0 1 1 1 1XXX 32 178000h to 17FFFFh 1 0 0 0 0XXX 32 180000h to 187FFFh 1 0 0 0 1XXX 32 188000h to 18FFFFh 1 0 0 1 0XXX 32 190000h to 197FFFh 1 0 0 1 1XXX 32 198000h to 19FFFFh 1 0 1 0 0XXX 32 1A0000h to 1A7FFFh 1 0 1 0 1XXX 32 1A8000h to 1AFFFFh 1 0 1 1 0XXX 32 1B0000h to 1B7FFFh 1 0 1 1 1XXX 32 1B8000h to 1BFFFFh 1 1 0 0 0XXX 32 1C0000h to 1C7FFFh 1 1 0 0 1XXX 32 1C8000h to 1CFFFFh 1 1 0 1 0XXX 32 1D0000h to 1D7FFFh 1 1 0 1 1XXX 32 1D8000h to 1DFFFFh 1 1 1 0 0XXX 32 1E0000h to 1E7FFFh 1 1 1 0 1XXX 32 1E8000h to 1EFFFFh 1 1 1 1 0XXX 32 1F0000h to 1F7FFFh 1 1 1 1 1XXX 32 1F8000h to 1FFFFFh 0 0 0 0 0XXX 32 200000h to 207FFFh 0 0 0 0 1XXX 32 208000h to 20FFFFh 0 0 0 1 0XXX 32 210000h to 217FFFh 0 0 0 1 1XXX 32 218000h to 21FFFFh 0 0 1 0 0XXX 32 220000h to 227FFFh 0 0 1 0 1XXX 32 228000h to 22FFFFh 0 0 1 1 0XXX 32 230000h to 237FFFh (Continued) 12 MBM29BS/FS12DH12 Sector Address Bank Sector SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 Bank Address A22 A21 A20 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Sector Size (x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 0 1 1 1XXX 32 238000h to 23FFFFh 0 1 0 0 0XXX 32 240000h to 247FFFh 0 1 0 0 1XXX 32 248000h to 24FFFFh 0 1 0 1 0XXX 32 250000h to 257FFFh 0 1 0 1 1XXX 32 258000h to 25FFFFh 0 1 1 0 0XXX 32 260000h to 267FFFh 0 1 1 0 1XXX 32 268000h to 26FFFFh 0 1 1 1 0XXX 32 270000h to 277FFFh 0 1 1 1 1XXX 32 278000h to 27FFFFh 1 0 0 0 0XXX 32 280000h to 287FFFh 1 0 0 0 1XXX 32 288000h to 28FFFFh 1 0 0 1 0XXX 32 290000h to 297FFFh 1 0 0 1 1XXX 32 298000h to 29FFFFh 1 0 1 0 0XXX 32 2A0000h to 2A7FFFh 1 0 1 0 1XXX 32 2A8000h to 2AFFFFh 1 0 1 1 0XXX 32 2B0000h to 2B7FFFh 1 0 1 1 1XXX 32 2B8000h to 2BFFFFh 1 1 0 0 0XXX 32 2C0000h to 2C7FFFh 1 1 0 0 1XXX 32 2C8000h to 2CFFFFh 1 1 0 1 0XXX 32 2D0000h to 2D7FFFh 1 1 0 1 1XXX 32 2D8000h to 2DFFFFh 1 1 1 0 0XXX 32 2E0000h to 2E7FFFh 1 1 1 0 1XXX 32 2E8000h to 2EFFFFh 1 1 1 1 0XXX 32 2F0000h to 2F7FFFh 1 1 1 1 1XXX 32 2F8000h to 2FFFFFh 0 0 0 0 0XXX 32 300000h to 307FFFh 0 0 0 0 1XXX 32 308000h to 30FFFFh 0 0 0 1 0XXX 32 310000h to 317FFFh 0 0 0 1 1XXX 32 318000h to 31FFFFh 0 0 1 0 0XXX 32 320000h to 327FFFh 0 0 1 0 1XXX 32 328000h to 32FFFFh 0 0 1 1 0XXX 32 330000h to 337FFFh 0 0 1 1 1XXX 32 338000h to 33FFFFh 0 1 0 0 0XXX 32 340000h to 347FFFh 0 1 0 0 1XXX 32 348000h to 34FFFFh 0 1 0 1 0XXX 32 350000h to 357FFFh 0 1 0 1 1XXX 32 358000h to 35FFFFh 0 1 1 0 0XXX 32 360000h to 367FFFh 0 1 1 0 1XXX 32 368000h to 36FFFFh (Continued) 13 MBM29BS/FS12DH12 (Continued) Sector Address Bank Sector SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank Address A22 A21 A20 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 Sector Size (x 16) Bank B Address Range A19 A18 A17 A16 A15 A14 A13 A12 (Kwords) 0 1 1 1 0XXX 32 370000h to 377FFFh 0 1 1 1 1XXX 32 378000h to 37FFFFh 1 0 0 0 0XXX 32 380000h to 387FFFh 1 0 0 0 1XXX 32 388000h to 38FFFFh 1 0 0 1 0XXX 32 390000h to 397FFFh 1 0 0 1 1XXX 32 398000h to 39FFFFh 1 0 1 0 0XXX 32 3A0000h to 3A7FFFh 1 0 1 0 1XXX 32 3A8000h to 3AFFFFh 1 0 1 1 0XXX 32 3B0000h to 3B7FFFh 1 0 1 1 1XXX 32 3B8000h to 3BFFFFh 1 1 0 0 0XXX 32 3C0000h to 3C7FFFh 1 1 0 0 1XXX 32 3C8000h to 3CFFFFh 1 1 0 1 0XXX 32 3D0000h to 3D7FFFh 1 1 0 1 1XXX 32 3D8000h to 3DFFFFh 1 1 1 0 0XXX 32 3E0000h to 3E7FFFh 1 1 1 0 1XXX 32 3E8000h to 3EFFFFh 1 1 1 1 0XXX 32 3F0000h to 3F7FFFh 1 1 1 1 1XXX 32 3F8000h to 3FFFFFh 14 MBM29BS/FS12DH12 Sector Address Table (Bank C) Sector Address Bank Sector SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 1 0 0 00000XXX 1 0 0 00001XXX 1 0 0 00010XXX 1 0 0 00011XXX 1 0 0 00100XXX 1 0 0 00101XXX 1 0 0 00110XXX 1 0 0 00111XXX 1 0 0 01000XXX 1 0 0 01001XXX 1 0 0 01010XXX 1 0 0 01011XXX 1 0 0 01100XXX 1 0 0 01101XXX 1 0 0 01110XXX 1 0 0 01111XXX 1 0 0 10000XXX 1 0 0 10001XXX 1 0 0 10010XXX 1 0 0 10011XXX 1 0 0 10100XXX 1 0 0 10101XXX 1 0 0 10110XXX 1 0 0 10111XXX 1 0 0 11000XXX 1 0 0 11001XXX 1 0 0 11010XXX 1 0 0 11011XXX 1 0 0 11100XXX 1 0 0 11101XXX 1 0 0 11110XXX 1 0 0 11111XXX 1 0 1 00000XXX 1 0 1 00001XXX 1 0 1 00010XXX 1 0 1 00011XXX 1 0 1 00100XXX 1 0 1 00101XXX 1 0 1 00110XXX Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh (Continued) Bank C 15 MBM29BS/FS12DH12 Sector Address Bank Sector SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 Bank Address A22 A21 A20 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 A19 A18 A17 A16 A15 A14 00111X 01000X 01001X 01010X 01011X 01100X 01101X 01110X 01111X 10000X 10001X 10010X 10011X 10100X 10101X 10110X 10111X 11000X 11001X 11010X 11011X 11100X 11101X 11110X 11111X 00000X 00001X 00010X 00011X 00100X 00101X 00110X 00111X 01000X 01001X 01010X 01011X 01100X 01101X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh 6D0000h to 5D7FFFh 6D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh (Continued) Bank C 16 MBM29BS/FS12DH12 (Continued) Bank Sector SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 Sector Address Bank Address A22 A21 A20 A19 A18 A17 A16 1 1 0 0111 1 1 0 0111 1 1 0 1000 1 1 0 1000 1 1 0 1001 1 1 0 1001 1 1 0 1010 1 1 0 1010 1 1 0 1011 1 1 0 1011 1 1 0 1100 1 1 0 1100 1 1 0 1101 1 1 0 1101 1 1 0 1110 1 1 0 1110 1 1 0 1111 1 1 0 1111 Sector Size A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X (x 16) Bank C Address Range A12 (Kwords) X 32 670000h to 677FFFh X 32 678000h to 67FFFFh X 32 680000h to 687FFFh X 32 688000h to 68FFFFh X 32 690000h to 697FFFh X 32 698000h to 69FFFFh X 32 6A0000h to 6A7FFFh X 32 6A8000h to 6AFFFFh X 32 6B0000h to 6B7FFFh X 32 8B8000h to 6BFFFFh X 32 6C0000h to 6C7FFFh X 32 6C8000h to 6CFFFFh X 32 6D0000h to 6D7FFFh X 32 6D8000h to 6DFFFFh X 32 6E0000h to 6E7FFFh X 32 6E8000h to 6EFFFFh X 32 6F0000h to 6F7FFFh X 32 6F8000h to 6FFFFFh 17 MBM29BS/FS12DH12 Sector Address Table (Bank D) Sector Address Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 Bank Address A22 A21 A20 A19 A18 A17 A16 A15 A14 1 1 1 00000X 1 1 1 00001X 1 1 1 00010X 1 1 1 00011X 1 1 1 00100X 1 1 1 00101X 1 1 1 00110X 1 1 1 00111X 1 1 1 01000X 1 1 1 01001X 1 1 1 01010X 1 1 1 01011X 1 1 1 01100X 1 1 1 01101X 1 1 1 01110X 1 1 1 01111X 1 1 1 10000X 1 1 1 10001X 1 1 1 10010X 1 1 1 10011X 1 1 1 10100X 1 1 1 10101X 1 1 1 10110X 1 1 1 10111X 1 1 1 11000X 1 1 1 11001X 1 1 1 11010X 1 1 1 11011X 1 1 1 11100X 1 1 1 11101X 1 1 1 11110X 1 1 1 111110 1 1 1 111110 1 1 1 111110 1 1 1 111110 1 1 1 111111 1 1 1 111111 1 1 1 111111 1 1 1 111111 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x 16) Address Range 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh 7D0000h to 7D7FFFh 7D8000h to 7DFFFFh 7E0000h to 7E7FFFh 7E8000h to 7EFFFFh 7F0000h to 7F7FFFh 7F8000h to 7F8FFFh 7F9000h to 7F9FFFh 7FA000h to 7FAFFFh 7FB000h to 7FBFFFh 7FC000h to 7FCFFFh 7FD000h to 7FDFFFh 7FE000h to 7FEFFFh 7FF000h to 7FFFFFh Bank D 18 MBM29BS/FS12DH12 Sector Group Address Table A19 A18 A17 A16 A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 (Continued) 19 MBM29BS/FS12DH12 Sector Group SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 A22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 X X X X X X X X X X X X X X X X X X X X X X X X A15 X X X X X X X X X X X X X X X X X X X X X X X X A14 X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134 SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174 (Continued) 20 MBM29BS/FS12DH12 (Continued) Sector Group SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 SGA68 SGA69 SGA70 SGA71 SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79 SGA80 SGA81 SGA82 SGA83 A22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sectors SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238 SA239 to SA242 SA243 to SA246 SA247 to SA250 SA251 to SA254 SA255 to SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 21 MBM29BS/FS12DH12 Common Flash Memory Interface Code Table A6 to A0 DQ15 to DQ0 Description 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0017h Description Query-unique ASCII string "QRY" Primary OEM Command Set 2h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VCC Max (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/ word write 2N s Typical timeout for Min size buffer write 2N s Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual block erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information A6 to A0 39h 3Ah 3Bh 3Ch 40h 41h 42h 43h 44h 45h DQ15 to DQ0 0000h 0000h 0000h 0000h 0050h 0052h 0049h 0031h 0033h 000Ch Erase Block Region 4 Information Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0h = Required 1h = Not Required Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write Sector Protection 0h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 00h = Not Supported 01h = Supported Sector Protection Algorithm Simultaneous Operation 00h = Not Supported, X = Total number of sectors in all Banks except Bank A Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported ACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV Boot Type Program Suspend 00h = Not Supported, 01h = Supported Bank Organization Bank A Region Information Bank B Region Information Bank C Region Information Bank D Region Information 46h 0002h 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 0019h 0000h 0000h 0004h 0000h 0009h 0000h 0004h 0000h 0004h 0000h 0018h 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 47h 0001h 48h 49h 0000h 0007h 4Ah 00E7h 4Bh 4Ch 0001h 0000h 4Dh 00B5h 4Eh 00C5h 4Fh 50h 57h 58h 59h 5Ah 0001h 0000h 0004h 0027h 0060h 0060h Erase Block Region 2 Information Erase Block Region 3 Information 5Bh 0027h 22 MBM29BS/FS12DH12 s FUNCTIONAL DESCRIPTION Asynchronous Read Operation (Non-Burst) Mode When the device first powers up, it is enabled for asynchronous read operation. CLK is ignored in this operation. To read data from the memory array, the system must first assert a valid address on A22 to A0, while driving AVD and CE to VIL. WE should remain at VIH. The addresses are latched on the falling edge of CE while AVD is held low or the address transition while AVD is held low. The data will appear on DQ15 to DQ0. Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output. The internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. During power transition RESET must be held low. (Refer to "Power On/Off Timing Diagram") This ensures that no spurious alteration of the memory content occurs during the power transition. Synchronous (Burst) Read Operation Mode The device is capable of linear burst operation of a preset length. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the configuration register set command sequence. See "Configuration Register Set Command" and "Command Definitions" for further details. Once the system has written the "Configuration Register Set" command sequence, the device Read mode is enabled for synchronous reads only. The initial word is output tIACC after the active edge of the first CLK cycle. Subsequent words are output tBACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. 8-, 16-, and 32-Word Linear Burst with Wrap Around The device provides Linear burst mode, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode. As an example: if the starting address in the 8-word with wrap-around mode is 39h, the address range to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. The RDY pin indicates when data is valid on the bus in synchronous read mode. The devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). Burst Address Groups Table Mode 8-word with wrap-around 16-word with wrap-around 32-word with wrap-around Group Size 8 words 16 words 32 words Group Address Ranges 0h-7h, 8h-Fh, 10h-17h, ... 0h-Fh, 10h-1Fh, 20h-2Fh, ... 00h-1Fh, 20h-3Fh, 40h-5Fh, ... 23 MBM29BS/FS12DH12 Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Burst Suspend / Resume The Burst Suspend / Resume feature allows the system temporarily suspend a synchronous burst operation during the initial access (before data is available) or after the device is outputting data. When the burst operation is suspended, any previously latched internal data and the current state are retained. At Handshaking mode, when the Burst Suspend is enabled the device will enter power down mode, in which the current consumption is reduced to typically 1mA. At Non-Handshaking mode, the device does not go to power down mode. Burst plus Burst Suspend should not last longer than tRCC without relaching an address or crossing address boundary. Burst Suspend requires CE to be asserted, WE deasserted, and the initial address latched by the CLK edge. Burst Suspend occurs when OE is deasserted. To resume the burst access, OE must be re-asserted. The next active CLK edge will resume the burst sequence where it had been suspended. The RDY pin is only controlled by CE. RDY will remain active and is not placed into a high-impedance state when OE is de-asserted. When using Burst Suspend feature, the host system should set the configuration register to "RDY active with data (A18=1)". Refer to "Configuration Register Set Command". Handshaking Option The device is equipped with a handshaking feature that brings out the fastest initial latency of this burst mode flash memory by simply monitoring the RDY signal from the device to determine when the initial word of burst data is ready to be read. In this handshaking mode, the microprocessor does not need to set its register the number of initial wait clocks. The device will indicate when the initial word of burst data is valid by the rising edge of RDY after OE goes low. The presence of the handshaking feature may be verified by writing the autoselect command sequence to the device. See "Autoselect Command Sequence" for details. For optimal burst mode performance on devices with the handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. See "Configuration Register Set Command" section for more information. Non-Handshaking Option In Non-Handshaking option, the device does not require the host system monitoring RDY signal. The microprocessor will know the number of initial wait count to be required by setting its own register. The device always provides initial data with same initial clock latency that is set by Configuration Register. See "Configuration Register Set Command" section for more information. Simultaneous Operation The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A22, A21, A20)with zero latency. The device consists of the following four banks : Bank A : 8 X 4 Kword and 31 X 32 Kword; Bank B : 96 X 32 Kword; Bank C : 96 X 32 Kword; Bank D : 8 X 4 Kword and 31 X 32 Kword. The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. (See "Burst Address Groups Table". ) This is what we call a "FlexBank", for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or erase) operation. However, the different types of operations for the three banks are impossible, e.g.Bank A writing, Bank B erasing, and Bank C reading out. With this "FlexBank", as described in "FlexBankTM Architecture Table",the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multi-function mode in the same bank. "Simultaneous Operation Table" shows the possible combinations for simultaneous operation. (Refer to "Bank-to-Bank Read/Write Timing Diagram" in "s TIMING DIAGRAM". ) 24 MBM29BS/FS12DH12 FlexBankTM Architecture Table Bank Splits 1 2 3 4 Bank 1 Volume 16 Mbit 48 Mbit 48 Mbit 16 Mbit Combination Bank A Bank B Bank C Bank D Volume 112 Mbit 96 Mbit 96 Mbit 112 Mbit Bank 2 Combination Remember (Bank B, C, D) Remember (Bank A, C, D) Remember (Bank A, B, D) Remember (Bank A, B, C) Bank Splits Example of Virtual Banks Combination Table Bank 1 Megabits Combination of Memory Bank Sector Sizes Megabits Bank 2 Sector Sizes Combination of Memory Bank Bank B + Bank C + Bank D Bank B + Bank C Bank A + Bank C + Bank D Bank C + Bank D 1 16 Mbit Bank A Eight 4K word, thirty-one 32K word 112 Mbit Eight 4K word, two hundred twentythree 32K word 2 32 Mbit Bank A + Bank D Sixteen 4K word, sixty-two 32K word 96 Mbit One hundred ninetytwo 32K word 3 48 Mbit Bank B Ninety-six 32K word 80 Mbit Sixteen 4K word, one hundred fiftyeight 32K word Eight 4K word, one hundred twentyseven 32K word 4 64 Mbit Bank A + Bank B Eight 4K word, one hundred twentyseven 32K word 64 Mbit Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected. ) Meanwhile the system would get to read from either Bank C or Bank D. Simultaneous Operation Table Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode Case 1 2 3 4 5 6 7 Bank 2 Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the Banks. 25 MBM29BS/FS12DH12 Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC0.2 V. Under this condition the current consumed is less than 10 A Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even if CE="H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS0.3 V (CE="H" or "L") . Under this condition the current consumed is less than 5A Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state, regardless of OE input. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC +60 ns. The automatic sleep mode is independent of the CE, WE, and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Under the mode, the current consumed is typically 0.2 A (CMOS Level). Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. While in synchronous mode, the device automatically enables this mode when the first active CLK level (if rising edge is acitive, the first period of CLK=VIH) is greater than tACC. During this mode on Handshaking devices, initial latency will be same between even and odd address. The device always outputs data with the same latency to even address. In case of Non-Handshaking devices, initial latecny is fixed same as normal operation. When the deivce is in the Automatic sleep mode, the device outputs burst data with the CLK. Please note that if CLK runs faster (active CLK level is shorter than tACC) during burst access in the Automatic speep mode, the device will output incorrect data. In this case, a new burst operations (addresses must be re-latched) is required to provide correct data. Under the mode, the current consumed is typically TBD A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Output Disable When the OE input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine output dictates the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. - At Asynchronous Mode Clock is ignored when the Configuration Register is set to Asynchronous mode, the device has the capability of performing two types of programming operation. WE latch - The system must drive CE, WE, and AVD to VIL and OE to VIH when providing an address and data. Addresses are latched on the falling edge of WE while data is latched on the rising edge of WE. (Refer to "Program Operation Timing at Asynchronous Mode (WE latch)"). AVD latch - The system must drive CE and AVD to VIL, and OE to VIH when providing an address to the device, and drive WE and CE to VIL, and OE to VIH when wiring data. Addresses are latched on the rising edge of AVD and data is latched on the rising edge of WE. (Refer to "Program Operation Timing at Asynchronous Mode (AVD latch)"). 26 MBM29BS/FS12DH12 - At Synchronous Mode When the Configuration Register is set to Synchronous mode, the device has the capability of performing two types of programming operation. WE latch - The system must drive CE, WE, and AVD to VIL and OE to VIH when providing an address and data. Addresses are latched on the falling edge of WE while AVD is held VIL and data is latched on the rising edge of WE. (Refer to "Program Operation Timing at Synchronous Mode (WE latch)"). Refer to AC Write Characteristics and the Erase/Program Waveforms for specific timing parameters. Note : Addresses are latched on the first of either the falling edge of WE or active edge of CLK. CLK latch - The system must drive CE and AVD to VIL, and OE to VIH when providing an address to the device, and drive WE and CE to VIL, and OE to VIH when wiring data. Addresses are latched on the active edge of clock while AVD is held VIL and data is latched on the rising edge of WE. (Refer to "Program Operation Timing at Synchronous Mode (CLK latch)"). RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional "tRH" before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. When at VIL, ACC locks all sectors. Should be at VIH for all other conditions. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the ACC pin returns the device to normal operation. Do not remove VACC from ACC pin while programming. See "Accelerated Fast mode Programming Timing" in "s TIMING DIAGRAM". HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped to the field. ONLY Program is possible in this area until it is protected. Once it is protected, it is impossible to unprotect, so please use this with caution. HiddenROM area is 128 words (64 words for factory and 64 words for customer) in length and is stored at the same address of the "outermost" 4 Kwords boot sector. The device occupies the address of the 000000h 00007Fh. After the system has written the Enter HiddenROM command sequence, the system may read the HiddenROM region by using the addresses normally occupied by the boot sector (particular area of SA0). That is, the device sends all commands that would normally be sent to the boot sector to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. 27 MBM29BS/FS12DH12 HiddenROM area is devided into two regions, which are Factory Locked area and Customer Locked area. The Factory Locked area is 64 words (address: 000000h - 00003Fh) that is programmed and locked at Fujitsu. The Customer Locked area is also 64 words (address: 000040h - 00007Fh) that is programmed and locked at user. The Factory indicator Bit (DQ7) is used to indicate whether or not the Factory Locked area is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Locked area is locked. The Factory Locked area can be programmed and protected at Fujitsu ONLY and is always protected when shipped from the factory regardless of the conditon whether or not this area is programmed. Therefore this area has the Factory Indicator Bit (DQ7) permanently set to a "1". The Factory Locked area cannot be modified in any way. The Customer Locked area is shipped unprotected, allowing users to utilize that area in any manner they choose. The Customer Indicator Bit set to "0". Once the Customer Locked area is protected, the Customer Indicator Bit will be permanently set to "1". MBM29BS/FS12DH12 dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DPBs maybe set or cleared as often as needed. PPB vs DPB The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the NonVolatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PBB Lock to disable any further changes to the PBBs during system operation. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DPB Write command sequence is all that is necessary. The DPB write/erase command for the dynamic sectors switch the DPBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. Note : to achieve the best protection, it's recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP = VIL. DPB 0 1 0 1 0 1 0 1 PPB 0 0 1 1 0 0 1 1 PPB Lock 0 0 0 0 1 1 1 1 Sector State Unprotected--PPB and DPB are changeable Protected--PPB and DPB are changeable Protected--PPB and DPB are changeable Protected--PPB and DPB are changeable Unprotected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable Protected--PPB not changeable, DPB is changeable The above table contains all possible combinations of the DPB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PBB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DPB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DPB, PPB, and PPB lock for a given sector can be verified by writing a DPB/PPB lock verify command to the device. 29 MBM29BS/FS12DH12 -DPB Status The programming of the DPB for a given sector can be verified by writing a DPB status verify command to the device. -PPB Status The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. -PPB Lock Bit Status The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command to the device. c) Persistent Protection Bit Lock (PPB Lock) * PPB Locked * PPB Locked with Password A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP and ACC Hardware Protection feature is always available, independent of the software managed protection method chosen. PPB lock bit is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit back to a "1". If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Sector Protection Mode. 30 MBM29BS/FS12DH12 -Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: (1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. (2) It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Veri fy Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. -Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. 31 MBM29BS/FS12DH12 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the reading. "MBM29BS/FS12DH Command Definitons Table" shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, verify mode of secter protect commands the Reset operation is initiated by writing the Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Asynchronous Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. Configuration Register Set Command The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode(burst length), active clock edge, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a three-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11 to A0 should be 555h, address bits A19 to A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or New Sector Protection). Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. Address A19 determines this setting: "1' for asynchronous mode, "0" for synchronous mode. Programmable Wait State Configuration Setting The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14 to A12 determine the setting (see "Third Cycle Address/Data Table"). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Third Cycle Address/Data Table A13 A12 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 A14 0 0 0 0 1 1 1 1 32 Total Initial Access Cycles 2 3 4 5 6 7 Reserved Reserved MBM29BS/FS12DH12 - Handshaking Option If the device is equipped with the handshaking option, the host system should set address bits (A14,A13, A12) = (0, 1, 0)for a clock frequency of 54/66/80MHz for the system/device to execute at maximum speed. The device will automatically delay RDY by one additional clock cycle when the starting address is odd. "Third Cycle Address/Data Table" describes the typical number of clock cycles (wait states) for various conditions. Wait States for Handshaking Table Conditions at Address Initial address is even Initial address is odd Typical No. of Clock Cycles after AVD Low 80/66/54 MHz 4 5 The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. See the "Autoselect Command" section for more information. - Non-Handshaking Option For optimal burst mode performance on devices without the handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. Wait States for Non-Handshaking Table Typical No. of Clock Cycles after AVD Low Conditions at Address 80/66/54 MHz Initial address is even Initial address is odd Burst Read Mode Configuration Setting(Burst Length) The device supports three different burst read modes: 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. For example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then advances to the next 8-word boundary. The address pointer then returns to the 1st word after the previous eight-word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. "Wait States for Handshaking Table" shows the address bits and settings for the three burst read modes. Burst Read Mode Settings Table Burst Modes 8-word linear wrap around 16-word linear wrap around 32-word linear wrap around Active Clock Edge Configuration Setting The device can be set so that either the rising clock edge or falling clock edge is active for all synchronous access. Address bit A17 determines this setting; "1" for rising active, "0" for falling active. Address Bits A16 0 1 1 A15 1 0 1 5 5 33 MBM29BS/FS12DH12 RDY Configuration Setting The device can be set so that RDY goes active either with valid data or one data cycle before active data. Address bit A18 determines this setting; "1" for RDY active with data, "0" for RDY active one clock cycle before valid data. "Configuration Register Table" shows the address bits that determine the configuration register settings for various device functions. Configuration Register Table Settings (Binary) 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK 00 = Reserved 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around Address BIt A19 A18 A17 A16 A15 A14 A13 Function Set Device Read Mode RDY Clock Burst Read Mode A12 000 = Data is valid on the 2th active CLK edge after AVD transition to VIH 001 = Data is valid on the 3th active CLK edge after AVD transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD transition to VIH Programmable 011 = Data is valid on the 5th active CLK edge after AVD transition to VIH Wait State 100 = Data is valid on the 6th active CLK edge after AVD transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD transition to VIH 110 = Reserved 111 = Reserved Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. The higher order address (A22, A21, A20) required for reading out the manufacture and device codes demands the bank address (BA) set at the third write cycle. Following the command write ,a read cycle from address (BA)00h returns the manufacturer's code (Fujitsu= 04h) . And a read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. (Refer to "MBM29BS/ FS12DH Sector Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in "s DEVICE BUS OPERATIION". ) The sector state (PPB protection or PPB unprotection) will be informed by address (BA) XX02h. Scanning the sector group addresses (A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while(A7, A6, A5, A4, A3, A2, A1,A0) = (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming 34 MBM29BS/FS12DH12 verification should be performed by verifying sector group protection on the protected sector. (See "MBM29BS/ FS12DH User Bus Operations Table" in "s DEVICE BUS OPERATIION". ) The manufacture and device codes can be read from the selected bank. To read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command sequence into the register. Autoselect command should then be written into the bank to be read. If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software. No subsequent data will be made available if the autoselect data is read in synchronous mode. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, Read/Reset command sequence must be written before the Autoselect command. Word Programming Command The device is programmed on word-by-word basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit). The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags Table"). Therefore, the device requires that a valid address to the device be supplied by the system in this particular instance. Hence, Data Polling must be performed at the memory location which is being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert from "0"s to "1"s. "Embedded ProgramTM Algorithm" in "s FLOW CHART" illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Command Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip erase begins on the rising edge of the last WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section. ) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) "Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 35 MBM29BS/FS12DH12 Sector Erase Command Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. After timeout of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29BS/FS12DH Command Definitions Table" in "s DEVICE BUS OPERATION". This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last WE will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer. ) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to Write Operation Status section for Sector Erase Timer operation. ) Loading the sector erase buffer may be done in any sequence and with any number of sectors. Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The sector erase begins after the "tTOW" time out from the rising edge of WE for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section. ) at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase. In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. "Embedded EraseTM Algorithm" in "s FLOW CHART" illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume Command The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are "DON'T CARES" when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from 36 MBM29BS/FS12DH12 sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2. ) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within Bank being programmed (erase-suspend program). To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode The device has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. Do not write any other commands, except Fast Program Command and Reset from Fast Program Command. The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to "Embedded Programming Algorithm for Fast Mode" in "s FLOW CHART". ) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to "Embedded Programming Algorithm for Fast Mode" in "s FLOW CHART". ) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interro gation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the Read/Reset command sequence into the register. HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. The HiddenROM area is 128 words (64 words for factory and 64 words for customer). This area is normally the "outermost" 4 Kwords boot block area in Bank A. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. The following commands are not allowed when the HiddenROM is enabled. 1. CFI 2. Set to Fast Mode 3. Fast Program 4. Reset from Fast Mode 5. Sector Erase Suspend 6. Sector Erase Resume 7. Chip Erase Command 37 MBM29BS/FS12DH12 HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, data of the address will be changed. HiddenROM Protect Command To protect the HiddenROM area, write the HiddenROM Protect command sequence during HiddenROM mode. After issuing "OPBP/48h" at 4th bus cycle, the device requires approximately 150us time out period for protecting HiddenROM area. Then by writing "OPBP/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then HiddenROM area is protected. If not, then the user needs to repeat this program sequence from the 4th cycle of "OPBP/48h". Password Program Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. 4 Password Program commands are required to program the password. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program Algorithm with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. Writing the HiddenROM Exit command returns the device back to normal operation. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1:A0) are valid during the Password Verify. Writing the HiddenROM Exit command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased and the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. After issuing "PL/68h" at 4th bus cycle, the device requires approximately 150s time out period for programming the Password Protection Mode Locking Bit. Then by writing "PL/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then Password Protection Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "PL/68h". Exiting the Password Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. After issuing "SPML/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the Persistent Protection Mode Locking Bit. Then by writing "SPML/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then Persistent Protection 38 MBM29BS/FS12DH12 Mode Locking Bit is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "SPML/68h". Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the HiddenROM Exit command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the HiddenROM Exit command. DPB Write(Erase) Command The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (A22 to A12) are issued at the same time as the code 01h or 00h on DQ7 to DQ0. All other DQ data bus pins are ignored during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DPBs are cleared at power-up or hardware reset. Exiting the DPB Write command is accomplished by writing the HiddenROM Exit command. DPB verify command DPB verify command is uesed to verify the status of a DPB for given sector. Scanning the sector addresses (SA) will produce a logical "1" at the device output DQ0 for a protected sector. Otherwise the device will produce "0" at DQ0 for the sector which is not protected. Writing the HiddenROM Exit Command returns the device back to normal operation. PPB Lock Bit verify command PPB Lock Bit verify command is used to verify the status of a PPB Lock Bit. A logical "1" at the device output DQ1 indicates that the PPB Lock Bit is set. If PPB Lock Bit is not set, DQ1 will output"0". Writing the HiddenROM Exit Command returns the device back to normal operation. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. A0 and A1 are used to determine the 16 bit data quantity is used to match separated 16 bits. Writing the Password Unlock command is address order specific. In other words, the lowers address A1:A0 = 00, the next cycle command is to A1:A0 = 01, then to A1:A0 = 10, and finally to A1:A0 = 11. Writing out of sequence results in the Password Unlock not returning a match with the password and the PPB Lock Bit remains set. Once the Password Unlock command is entered, the RY/BY pin goes LOW indicating that the device is busy. Also, reading the Bank A results in the DQ6 pin toggling, indicating that the Password Unlock function is in progress. Reading the other bank returns actual array data. Approximately 2s is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY is not driven and DQ6 does not toggle when read), the next cycle is issued, only this time with the next part of the password. Seven cycles Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock cycles, the order, and when to read the PPB Lock bit to confirm successful password unlock. Writing the HiddenROM Exit Command returns the device back to normal operation. 39 MBM29BS/FS12DH12 PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A22 to A12) are written at the same time as the program command 60h. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After issuing "SGA+WP/68h" at 4th bus cycle, the device requires approximately 150s time out period for programming the PPB. Then by writing "SGA+WP/48h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=1 then PPB is programmed. If not, then the user needs to repeat this program sequence from the 4th cycle of "SGA+WP/68h". The PPB Program command does not follow the Embedded Program algorithm. Writing the HiddenROM Exit Command returns the device back to normal operation. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h), all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After issuing "WP/60h" at 4th bus cycle, the device requires approximately 1.5ms time out period for programming the PPB. Then by writing "SGA+WP/40h" at 5th bus cycle, the device outputs verify data at DQ0. If DQ0=0 then PPB is successfully erased. If not, then the user needs to repeat this program sequence from the 4th cycle of "WP/60h". It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. Writing the HiddenROM Exit Command returns the device back to normal operation. WRITE OPERATION STATUS Detailed in "Hardware Sequence Flags Table" are all the status flags which can determine the status of the bank for the current mode operation. The read operation from the bank which doesn't operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1] and [3]. 40 MBM29BS/FS12DH12 Hardware Sequence Flags Table DQ6 DQ7 DQ7 0 1 Data DQ7 DQ7 Toggle Toggle No Toggle *3 Data Toggle Toggle Toggle Toggle 1 1 1 Status Embedded Erase Algorithm In Progress DQ5 0 0 0 Data 0 0 1 0 DQ3 0 1 0 Data 0 DQ2 No Toggle*3 Toggle*1 No Toggle*3 Toggle Data No Toggle*2,*3 No Toggle*3 N/A N/A Embedded Program Algorithm Erase Sector Non-Erase Sector Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm 0 Exceeded Time Limits Erase Erase Suspend Program Suspended DQ7 (Non-Erase Suspended Sector) Mode *1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. *2: Reading from non-erase suspend sector address will indicate logic "1" at the DQ2 bit. *3: When the device is se to Asynchronous mode, these status flags should be read by CE toggle. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device will produce a "1" on DQ7. The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm" in "s FLOW CHART". For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant, and then that byte's valid data at the next instant. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to DQ7 will be read on successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table". ) See "Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm) " and "Synchronous Data Polling Timings/Toggle Bit Timings" in "s TIMING DIAGRAM" for the Data Polling timing specifications and diagrams. 41 MBM29BS/FS12DH12 DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE toggling) data from the busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. CE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE must be high when bank address is changed. See "Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm) " and "Synchronous Data Polling Timings/Toggle Bit Timings" in "s TIMING DIAGRAM" for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce "1". This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in "MBM29BS/FS12DH User Bus Operations Table" in "s DEVICE BUS OPERATIION". The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset device with the command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to determine whether the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun. If DQ3 is low ("0") , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Configuration Register Table" : Hardware Sequence Flags. 42 MBM29BS/FS12DH12 DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not. ) See also "Hardware Sequence Flags Table". Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to "Toggle Bit Algorithm" in "s FLOW CHART". ) RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. In Synchronous mode RDY functions only data valid indicator. The RDY output to be low during the initial access in burst mode. When the device is configured in Asynchronous mode, the RDY is an open-drain output which indicates whether an Embedded Alogorithm is in progress or completed (RY/BY). If output is low, the device is busy with either a program or erase operation. If output is high (RY/BY should be pulled up), the device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, RDY output will be high-z. During programming at Asynchronous mode, the RDY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RDY pin will indicate a busy condition during RESET pulse. Since this is an open-drain output at Asynchronous mode, RDY pins can be tied together in parallel with a pullup resistor to VCCQ. 43 MBM29BS/FS12DH12 Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequence. Device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. 44 MBM29BS/FS12DH12 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All inputs and I/Os pins except as noted below*1,*2 Power Supply Voltage*1 I/O's Power Supply Voltage ACC* * 1, 3 Symbol Tstg TA VIN, VOUT VCC VCCQ VACC Rating Min -55 -40 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCCQ+0.5 +2.5 +2.5 +10.5 Unit C C V V V V *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on ACC pin is -0.5 V. During voltage transitions, ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +8.0 V. Maximum DC input voltage on ACC pin is +10.5 V which may overshoot to +12.5 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage* VCCQ Supply Voltage* Symbol TA VCC VCCQ Part No. MBM29BS/FS12DH 12 MBM29BS/FS12DH 12 MBM29BS/FS12DH 12 Value Min -40 +1.65 +1.65 Max +85 +1.95 +VCC Unit C V V * : Voltage is defined on the basis of VSS = GND = 0 V. Notes:Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 45 MBM29BS/FS12DH12 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns Figure 1 Maximum Undershoot Waveform 20 ns VCC +2.0 V VCC +0.5 V +1.0 V 20 ns 20 ns Figure 2 Maximum Overshoot Waveform 1 46 MBM29BS/FS12DH12 s DC CHARACTERISTICS * CMOS Compatible Parameter Input Leakage Current Output Leakage Current VCC Active Burst Read Current VCC Active Asynchronous Read Current*1 VCC Active Current*2 VCC Current (Standby) VCC Current (Standby, Reset)*3 VCC Current (Automatic Sleep Mode) VCC Active Current (Read-While-Program )*4 VCC Active Current (Read-While-Erase)*4 Input Low Level Input High Level Output Low Voltage Level Output High Voltage Level Voltage for ACC Program Acceleration*5 Symbol ILI ILO ICCB ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH VACC Conditions VIN = VSS to Vcc, VCC = Vcc Max VOUT = VSS to Vcc, VCC = Vcc Max CE = VIL, OE = VIH, WE = VIH, 80 MHz CE = VIL, OE = VIH, 10 MHz WE = VIH 5 MHz CE = VIL, OE = VIH, VPP = VIH CE = RESET = VCC 0.2 V RESET = VSSQ 0.2 V, CLK = VIL VCC = VCC Max, CE = VSSQ 0.2 V, RESET = VCCQ 0.2 V, VIN = VCCQ 0.2 V or VSSQ 0.2 V CE = VIL, OE = VIH CE = VIL, OE = VIH VCCQ = 1.8 V VCCQ = 1.8 V IOL = 100 A, VCC = VCC Min = VCCQ IOH = -100 A, VCC = VCC Min = VCCQ -- Value Min -- -- -- -- -- -- -- -- -- -- -0.5 VCCQ-0.4 -- VCCQ -0.1 8.5 Typ -- -- 15 20 10 15 0.2 0.2 0.2 25 25 -- -- -- -- -- Max 1.0 1.0 30 30 15 40 10 10 10 60 60 0.4 VCCQ+0.4 0.1 -- 9.5 Unit A A mA mA mA A A A mA mA V V V V V *1: The lCC current listed includes both the DC operating current and the frequency dependent component. *2: lCC active while Embedded Algorithm (Program or Erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remain stable for tACC + 60 ns. *4: Embedded Algorithm (Program or Erase) is in progress. (@5 MHz) *5: Applicable for only VCC. 47 MBM29BS/FS12DH12 s AC CHARACTERISTICS * Synchronous/Burst Read Parameter Latency (Even Address in Handshake Mode) Latency--(Non-Handshake or Odd Address in Handshake mode) Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK* Address Hold Time from CLK* Data Hold Time from Next Clock Cycle Chip Enable to RDY Valid Output Enable to Output Valid Chip Enable to High-Z Output Enable to High-Z CE# Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD Set Up Time to CLK AVD Hold Time to CLK Access Time CLK to access resume CLK to High-Z Output Enable Setup Time Read Cycle for Continuous suspend Read Cycle Time *: Addresses are latched on the active edge of CLK. Note : Test Conditions: Output Load: VCCQ = 1.65 V to 1.95 V : 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCQ Timing measurement reference level Input: 0.5 x VCCQ Output: 0.5 x VCCQ Symbols Value 54 MHz Max 69 87.5 13.5 -- -- -- 13.5 13.5 10 10 -- 13.5 -- -- -- 55 13.5 10 -- 1 -- 66 MHz Min -- -- -- 4 6 3 -- -- -- -- -- -- 0 4 6 -- -- -- 4 -- 50 Max 56 71 11 -- -- -- 11 11 8 8 4 11 -- -- -- 50 11 8 -- 1 -- 80 MHz Min -- -- -- 4 5.5 3 -- -- -- -- -- -- 0 4 5.5 -- -- -- 4 -- 45 Max 46 58.5 8.5 -- -- -- 8.5 8.5 8 8 4 8.5 -- -- -- 45 8.5 8 -- 1 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Unit JEDEC Standard Min tIACC tIACC tBACC tACS tACH tBDH tCR tOE tCEZ tOEZ tCES tRACC tCAS tAVSC tAVHC tACC tCKA tCKZ tOES tRCC tRC -- -- -- 5 7 4 -- -- -- -- 5 -- 0 5 7 -- -- -- 5 -- 55 48 MBM29BS/FS12DH12 * Asynchronous Read Value Symbols Parameter JEDEC Standard Read Cycle Time Access Time from CE Low Asynchronous Access Time* Output Enable to Output Valid Output Read Enable Hold Time Toggle and Data Polling Chip Enable to High-Z CE High During Toggle Bit Polling Output Enable to High-Z -- -- -- -- -- -- -- -- tRC tCE tACC tOE tOEH 10 tCEZ tCEPH tOEZ -- 20 -- -- 10 -- 10 8 -- 20 -- -- 8 -- 8 8 -- 20 -- -- 8 -- 8 ns ns ns ns 54 MHz Min 55 -- -- -- 0 Max -- 55 55 13.5 -- 66 MHz Min 50 -- -- -- 0 Max -- 50 50 11 -- 80 MHz Min 45 -- -- -- 0 Max -- 45 45 8.5 -- ns ns ns ns ns Unit * : Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD. * Hardware Reset (RESET) Parameter RESET Pin Low (During Embedded Algorithms) to Read Mode RESET Pulse Width Reset High Time Before Read Power On/Off Time Symbols JEDEC -- -- -- -- Standard tREADY tRP tRH tPS All Speed Options -- 500 200 0 20 -- -- -- Unit s ns ns ns 49 MBM29BS/FS12DH12 * Write (Erase/Program) Operations Parameter Write Cycle Time Address Setup Time Address Hold Time AVD Low Time CE Low to AVD High Data Setup Time Data Hold Time Read Recovery Time Before Write CE Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation Sector Erase Operation* VACC Rise and Fall Time VACC Setup Time (During Accelerated Programming) VCC Setup Time CE Setup Time to WE AVD Set Up Time to CLK AVD Hold Time to CLK AVD Setup Time to WE AVD Hold Time to WE Address Setup Time to CLK Address Hold Time to CLK Address Setup Time to AVD Address Hold Time to AVD WE Low to CLK AVD High to WE Low CLK to WE Low Erase Time-out TIme Symbols Value 54 MHz 55 0 20 12 12 45 0 0 0 30 20 0 -- -- 500 1 50 0 5 7 5 7 5 7 5 7 0 5 5 50 -- -- -- -- -- -- -- -- -- -- -- -- 6 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 0 20 10 10 20 0 0 0 20 20 0 -- -- 500 1 50 0 4 6 4 6 4 6 4 6 0 5 5 50 66 MHz -- -- -- -- -- -- -- -- -- -- -- -- 6 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 45 0 20 10 10 20 0 0 0 20 20 0 -- -- 500 1 50 0 4 5.5 4 5.5 4 5.5 4 5.5 0 5 5 50 80 MHz -- -- -- -- -- -- -- -- -- -- -- -- 6 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns s s ns s s ns ns ns ns ns ns ns ns ns ns ns ns s JEDEC Standard Min Typ Max Min Typ Max Min Typ Max tAVAV tAVWL tWLAX -- -- tDVWH tWHDX tGHWL tWHEH tEHWH tWHWL -- tWHWH1 tWHWH2 -- -- -- tELWL -- -- -- -- -- -- -- -- -- -- -- -- tWC tAS tAH tAVDP tCLAH tDS tDH tGHWL tCH tWP tWPH tSR/W tWHWH1 tWHWH2 tVID tVIDS tVCS tCS tAVSC tAVHC tAVSW tAVHW tACS tACH tAAS tAAH tWLC tAHWL tCWL tTOW *: Does not include the preprogramming time. Note : See the "Erase and Programming Performance" section for more information.1. 50 MBM29BS/FS12DH12 s ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycles -- -- -- 100,000 Typ 0.5 6.0 25.2 -- Max 2 100 95 -- s s s cycle Excludes programming prior to erasure Excludes system level overhead Excludes system level overhead Unit Comments Note : Test conditions TA = +25C, Typical Erase conditions TA = +25C, VCC = 1.8 V, Typical Program conditions TA = +25C, VCC = 1.8 V, Data = checker s FBGA PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF Note : Test conditions TA = +25C, f = 1.0 MHz 51 MBM29BS/FS12DH12 s TIMING DIAGRAM * Key to Switching Wavwforms WAVEFORM INPUTS Steady OUTPUTS Steady Change from H to L Change from H to L Change from L to H Change from L to H Don't Care Any Change Permitted Does Not Apply Changing, State Unknown Center Line is HighImpedance State(High-Z) 7 cycles for initial access shown. tCES tCEZ 2 3 4 5 6 7 CE 1 CLK tAVSC AVD tACS tAVHC tBDH Aa tACH tBACC High-Z tIACC tACC tCKA tRACC High-Z Da Da + 1 Da + n A22 to A0 DQ15 to DQ0 OE tCR tOES RDY High-Z Notes : * Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. * The device is in synchronous mode. Figure 3 Synchronous Burst Mode Read (Latched By Rising Active CLK) 52 MBM29BS/FS12DH12 4 cycles for initial access shown. tCES tCEZ CE 1 2 3 4 5 CLK tAVSC AVD tAVHC tACS tBDH Aa tACH tBACC High-Z tIACC tACC tOES Da Da + 1 Da + n A22 to A0 DQ15 to DQ0 OE tCR High-Z tCKA tRACC High-Z RDY Notes : * Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. * The device is in synchronous mode. Figure 4 Synchronous Burst Mode Read (Latched By Falling Active CLK) 53 MBM29BS/FS12DH12 CE CLK tAVSC tCES 1 2 7 cycles for initial access shown. 3 4 5 6 7 AVD tACS tAVHC tBDH Aa tACH tBACC tIACC tACC tCKA tRACC D0 D1 D2 D3 D4 D5 D6 D7 tCEZ A22 to A0 DQ15 to DQ0 OE RDY High-Z tOES tCR Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register command sequence has been written with A18 = 1; device will output RDY with valid data. Figure 5 8-word Linear Burst 54 MBM29BS/FS12DH12 CE CLK tAVSC tCES 1 2 7 cycles for initial access shown. 3 4 5 6 7 AVD tACS tAVHC tBDH Aa tACH tBACC tIACC tACC tCKA tRACC D6 D7 D0 D1 D2 D3 D4 D5 tCEZ A22 to A0 DQ15 to DQ0 OE RDY High-Z tOES tCR Note : Figure assumes 7 wait states for initial access, synchronous read. D0 to D7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in range (A6). See "Requirements for Synchronous (Burst) Read Operation". The Set Configuration Register command sequence has been written with A18 = 1; device will output RDY with valid data. Figure 6 8-word Linear Burst with Wrap Around 55 MBM29BS/FS12DH12 6 wait cycles for initial access shown. CE CLK tAVSC tCES 1 2 3 4 5 6 tCEZ AVD tACS tAVHC tBDH Aa tACH tBACC High-Z tIACC tOES tACC tCKA D0 tRACC High-Z D1 D2 D3 Da + n A22 to A0 DQ15 to DQ0 OE tCR RDY High-Z Note : Figure assumes 6 wait states for initial access, 66 MHz clock, and synchronous read. The Set Configuration Register command sequence has been written with A18 = 0; device will output RDY one cycle before valid data. Figure 7 Linear Burst with RDY Set One Cycle Before Data 56 MBM29BS/FS12DH12 Suspend CLK VIH Resume AVD Address tOES tOES OE tCKZ tCKA Data D20 tRACC tRACC D20 D21 D22 D23 tRACC D23 tRACC D23 D24 RDY CE VIL Note : Figure is for any even address other than 3Eh (or multiple thereof). The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. When the Burst Suspend is enabled the device will enter power down mode. Figure 8 Handshake Mode Burst Suspend at an even address 57 MBM29BS/FS12DH12 Suspend CLK VIH Resume AVD Address tOES tOES OE tCKZ tCKA Data D23 tRACC tRACC D23 D24 D25 tRACC D25 tRACC D25 D26 D27 RDY CE VIL Note : Figure is for any odd address other than 3Fh (or multiple thereof). The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. When the Burst Suspend is enabled the device will enter power down mode. Figure 9 Handshake Mode Burst Suspend at an odd address 58 MBM29BS/FS12DH12 1 2 3 4 Suspend 5 6 7 Resume CLK AVD Address A(0) tOES OE tCKA Data tRACC D(0) D(1) D(2) D(3) tRACC D(3) tRACC D(3) D(4) RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The starting address is Even. The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. When the Burst Suspend is enabled the device will enter power down mode. Figure 10 Handshake Mode Burst Suspend prior to Initial Access when the starting address is Even 59 MBM29BS/FS12DH12 1 2 3 4 Suspend 5 6 7 Resume CLK AVD Address A(1) tOES OE tCKA Data tRACC D(1) D(2) D(3) D(3) tRACC D(3) tRACC D(4) D(5) RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The starting address is Odd. The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. When the Burst Suspend is enabled the device will enter power down mode. Figure 11 Handshake Mode Burst Suspend prior to Initial Access when the starting address is Odd 60 MBM29BS/FS12DH12 Suspend CLK VIH Resume AVD Address tOES tOES OE tCKZ tCKA Data D20 tRACC tRACC D20 D21 D22 D23 D24 D25 D26 RDY CE VIL Note : The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. Figure 12 No-Handshake Mode Burst Suspend 61 MBM29BS/FS12DH12 1 2 3 4 Suspend 5 6 7 Resume CLK AVD Address A(n) tOES OE tCKA Data tRACC D(n) D(n+1) D(n+2) D(n+3) D(n+4) RDY CE Note : Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. Figure 13 No-Handshake Mode Burst Suspend prior to Initial Access 62 MBM29BS/FS12DH12 1 2 3 4 Suspend 5 6 7 Resume CLK tRCC AVD Address A(n) tOES OE tCKA tRCC Data D(n) Invalid Data RDY CE Notes : * Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence must be written with A18=1; device will output RDY with valid data. The clock during Burst Suspend is Don't care. * Burst plus Burst Suspend should not last longer than tRCC without relaching an address. After the period of tRCC the device will output invalid data. Figure 14 Read Cycle for No-Handshake Mode Continuous Suspend 63 MBM29BS/FS12DH12 tRC Address tACC Address Stable CE tOE tCEZ OE tOEZ tOEH WE tCE High-Z tOH High-Z Outputs Outputs Valid Notes : * AVD is assumed to be VIL. * Configuration Register is set to Asynchronous mode. Figure 15 Asynchronous Mode Read 64 MBM29BS/FS12DH12 CE, OE tRH RESET tRP Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms CE, OE tREADY RESET tRP Figure 16 Reset Timings tPS tPS RESET VCC 0V 1.65 V 1.65 V Address Valid Data In Data Valid Data Out tRH tACC Figure 17 Power On/Off Timings 65 MBM29BS/FS12DH12 Program Command Sequence (last two cycles) Read Status Data CLK tAVSW tAVHW AVD VIL 3rd Bus Cycle Data Polling PA tAH PA VA tRC tOH Address 555h tWC tAS tDS tDH Data A0h PD DQ7 DOUT tCEZ DOUT CE tCS tCH tOEZ tCE OE tGHWL tWP tWPH tOE tWHWH1 WE Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation. * A22 to A12 are don't care during command sequence unlock cycles. * CLK is Don't care. * Configuration Register is set to Asynchronous mode. Figure 18 Program Operation Timings at Asynchronous Mode (WE latch) 66 MBM29BS/FS12DH12 Program Command Sequence (last two cycles) Read Status Data CLK tCLAH AVD tAAH tAAS tAVDP Address Data 555h PA VA In Progress VA A0h tDS tDH PD Complete CE OE WE tCH tAHWL tWP tWHWH1 tWPH tWC tVCS tCS VCC Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation. * A22 to A12 are don't care during command sequence unlock cycles. * CLK is Don't care. * Configuration Register is set to Asynchronous mode. * Addresses are latched on the rising edge of AVD. Figure 19 Program Operation Timings at Asynchronous Mode (AVD latch) 67 MBM29BS/FS12DH12 Program Command Sequence (last two cycles) Read Status Data CLK tAVSW tAVHW AVD Address Data 555h tAS tAH A0h PA VA In Progress tDH VA PD tDS Complete CE OE WE tWLC tWP tCH tWPH tCS tWC tWHWH1 tVCS VCC Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation. * A22 to A12 are don't care during command sequence unlock cycles. * Configuration Register is set to Synchronous mode. * Addresses are latched on the first of either the falling edge of WE or active edge of CLK. When "tWLC" is not met then AVD/address set up and hold time to CLK will be required. Figure 20 Program Operation Timings at Synchronous Mode (WE latch) 68 MBM29BS/FS12DH12 Program Command Sequence (last two cycles) Read Status Data CLK tACS tACH tAVSC tAVHC CE AVD Address Data tCAS 555h PA VA In Progress VA A0h tDS tDH PD Complete OE WE tCWL tWP tCH tWHWH1 tVCS tWPH tWC Vcc Notes : * PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. * "In progress" and "complete" refer to status of program operation. * A22 to A12 are don't care during command sequence unlock cycles. * Configuration Register is set to Synchronous mode. * Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD. Figure 21 Program Operation Timings at Synchronous Mode (CLK latch) 69 MBM29BS/FS12DH12 Program Command Sequence (last two cycles) Read Status Data CLK tAVSW tAVHW AVD Address Data 2AAh tAS tAH 55h SA 555h for chip erase VA 10h for chip erase 30h tDS tDH In Progress VA Complete CE OE WE tWLC tWP tCH tWPH tCS tWC tWHWH2 tVCS VCC Notes : * SA is the sector address for Sector Erase. * Address bits A22 to A12 are don't cares during unlock cycles in the command sequence. * This timing is for Synchronous mode. Figure 22 Chip/Sector Erase Command Sequence 70 MBM29BS/FS12DH12 CE AVD WE Address Data Don't Care A0h PA Don't Care PD Don't Care OE ACC VID tVID VIL or VIH tVIDS Note : Use setup and hold times from conventional program operation. Figure 23 Accelerated Fast mode Programming Timing 71 MBM29BS/FS12DH12 AVD tCE tCEZ CE tCH tOE tOEZ OE tOEH WE tACC Address VA VA Status Data Status Data Notes : * Status reads in figure are shown as asynchronous mode. * VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data Polling will output true data and the toggle bits will stop toggling. Figure 24 Data Polling Timings/Toggle Bit Timings (During Embedded Algorithm) 72 MBM29BS/FS12DH12 CE CLK AVD Address OE tIACC tIACC Status Data Status Data VA VA Data RDY Notes : * The timings are similar to synchronous read timings. * VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. * RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode Configuration Register, RDY is active one clock cycle before data. Figure 25 Synchronous Data Polling Timings/Toggle Bit Timings 73 MBM29BS/FS12DH12 Data D0 D1 AVD Rising edge of next clock cycle following last wait state triggers next burst data total number of clock cycles following AVD falling edge OE 1 2 3 4 5 6 7 CLK 0 1 2 3 4 5 number of clock cycles programmed Wait State Decoding Addresses: A14, A13, A12 = "101" 5 programmed, 7 total A14, A13, A12 = "100" 4 programmed, 6 total A14, A13, A12 = "011" 3 programmed, 5 total A14, A13, A12 = "010" 2 programmed, 4 total A14, A13, A12 = "001" 1 programmed, 3 total A14, A13, A12 = "000" 0 programmed, 2 total Note : Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to "101". Figure 26 Example of Wait States Insertion (Non-Handshaking Device) 74 MBM29BS/FS12DH12 Last Cycle in Program or Sector Erase Command Sequence tWC Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tRC tCEPH tRC tWC CE OE tOE tOEH tGHWL WE tWPH tWP tDS tDH tACC tOEZ tOEH RD tSR/W RA RA 555h RD AAh Data tAS tAH PD/30h Address PA/SA AVD Note : Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information. Figure 27 Bank-to-Bank Read/Write Cycle Timings 75 MBM29BS/FS12DH12 Power-up/ Hardware Reset Asynchronous Read Mode Only Set Burst Mode Configuration Register Command for Synchronous Mode (A19 = 0) Set Burst Mode Configuration Register Command for Asynchronous Mode (A19 = 1) Synchronous Read Mode Only Figure 28 Synchronous/Asynchronous State Diagram 76 MBM29BS/FS12DH12 s FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Device Embedded Program Algorithm in progress Verify Data ? Yes No No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Figure 29 Embedded ProgramTM Algorithm 77 MBM29BS/FS12DH12 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling or Toggle Bit from Device No Data = FFh ? Yes Erasure Completed Embedded Erase Algorithm in progress Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address/30h Sector Address/30h Additional sector erase commands are optional. Sector Address/30h Notes : * See "MBM29BS/FS12DH Command Definitions" in "s DEVICE BUS OPERATION" for erase command sequence. * See the section on DQ3 for information on the sector erase timer. Figure 30 Embedded EraseTM Algorithm 78 MBM29BS/FS12DH12 Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA Yes VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 31 Data Polling Algorithm 79 MBM29BS/FS12DH12 Start Read DQ 7 to DQ 0 Addr. = VA *1 Read DQ 7 to DQ 0 Addr. = VA *1 DQ 6 = Toggle? Yes No No VA = Bank address being executed Embedded Algorithm DQ 5 = 1? Yes Read DQ 7 to DQ 0 Addr. = VA *1,*2 Read DQ 7 to DQ 0 Addr. = VA *1,*2 DQ 6 = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to "1". Figure 32 Toggle Bit Algorithm 80 MBM29BS/FS12DH12 FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXXh/A0h Program Address/Program Data Data Polling Device In Fast Program Verify Data? Yes No Increment Address Last Address ? Yes Programming Completed No XXXXh/90h Reset Fast Mode XXXXh/F0h Figure 33 Embedded Programming Algorithm for Fast Mode 81 MBM29BS/FS12DH12 s ORDERING INFORMATION Part No. MBM29BS/FS12DH12PBT Package 80-ball plastic FBGA (BGA-80P-M04) Access Time(ns) 12 Remarks MBM29BS/FS12 D H 12 PBT PACKAGE TYPE PBT = 80-Ball Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION Boot Sector Architecture D = Dual Boot Type DEVICE NUMBER/DESCRIPTION MBM29BS12 128 Mega-bit (8M x 16-Bit) Burst Mode Flash Memory 1.8 V-only Read, Write, and Erase with Non-Handshake MBM29FS12 128 Mega-bit (8M x 16-Bit) Burst Mode Flash Memory 1.8 V-only Read, Write, and Erase with Handshake 82 MBM29BS/FS12DH12 s PACKAGE DIMENSIONS 80-ball plastic FBGA (BGA-80P-M04) 11.000.10(.433.004) 1.08 -0.13 .043 -.005 +0.12 +.005 (Mounting height) B 0.40(.016) REF 0.80(.031) REF 0.380.10 (Stand off) (.015.004) A 8.000.10 (.315.004) 0.10(.004) S (INDEX AREA) S 8 7 6 5 4 3 2 1 MLKJHGFEDCBA (INDEX AREA) 80-o0.450.05 (80-o.018.002) 0.08(.003) M SAB C 2003 FUJITSU LIMITED B80004S-c-1-1 Dimensions in mm (inches) Note : The values in parentheses are reference values. 83 MBM29BS/FS12DH12 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0309 (c) FUJITSU LIMITED Printed in Japan |
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